In recent years, as a semiconductor device having a trench element isolation structure, a semiconductor device having a STI (Shallow Trench Isolation) structure or a DTI (Deep Trench Isolation) structure has attracted attention.
FIG. 29 is a schematic plan view illustrating the configuration of a semiconductor device 10 having a STI structure in the related art. FIG. 30 is a schematic sectional view taken along line A-A of the semiconductor device 10 of FIG. 29. FIG. 31 is a schematic sectional view taken along line B-B of the semiconductor device 10 of FIG. 29. FIG. 32 is a schematic plan view illustrating a main transistor and a parasitic transistor of the semiconductor device 10 of FIG. 29. FIG. 33 is a circuit diagram illustrating a relationship between the main transistor and the parasitic transistor of the semiconductor device 10 of FIG. 29. FIG. 34 is a graph showing a gate-source voltage (Vgs)-drain current (Id) characteristic of the semiconductor device 10 of FIG. 29.
Hereinafter, the semiconductor device 10 having a STI structure in the related art will be described with reference to the drawings. In FIGS. 29 to 32, as indicated by arrows X, Y and Z, three mutually orthogonal directions are defined as X, Y and Z directions, respectively. Throughout these figures, elements and parts or portions having the same functions may be denoted by the same reference numerals or symbols and explanation of which will not be repeated for the purpose of brevity and clarity.
As illustrated in FIG. 29, the semiconductor device 10 forms a transistor including an element isolation region 11 made of an insulating material, a source region 12, a drain region 13, a gate electrode 14, a semiconductor region 15 and a gate insulating film 16.
The semiconductor region 15 is a region on which the source region 12 and the drain region 13 are formed and also a region which is surrounded by the element isolation region 11. In a case of forming an NMOS transistor, the semiconductor region 15 is formed of the same P-type region as a silicon substrate.
The drain region 13 is formed in a substantially rectangular shape on a main surface of the semiconductor region 15. A long side of the drain region 13 extends in the Y direction, that is, the direction of a channel width W1 and channel a width W2 and a short side thereof extends in the X direction, that is, the direction of a channel length L1. An end portion of the drain region 13 in the Y and X directions is in contact with the element isolation region 11.
The source region 12 is formed in a substantially rectangular shape on the main surface of the semiconductor region 15 at a predetermined interval in the X direction with respect to the drain region 13. A long side of the source region 12 extends in the Y direction and a short side thereof extends in the X direction. An end portion of the source region 12 in the Y and X directions is in contact with the element isolation region 11, like the drain region 13.
The channel width W1 of the source region 12 in the Y direction and the channel width W2 of the drain region 13 in the Y direction are determined by the shape of the element isolation region 11. In typical, the channel width W1 and the channel width W2 are made approximately equal to each other. The length L1 from the end portion of the source region 12 to the end portion of the drain region 13 is typically called a channel length.
The element isolation region 11 is formed on the main surface of the semiconductor region 15 and inside the semiconductor region 15 so as to surround the source region 12 and the drain region 13.
The gate insulating film 16 is formed in a substantially rectangular shape on an upper portion of the semiconductor region 15 between the source region 12 and the drain region 13. Both end portions of the gate insulating film 16 in the Y direction are connected to the element isolation region 11. One end portion of the gate insulating film 16 in the X direction substantially overlaps the source region 12. The other end portion of the gate insulating film 16 in the X direction substantially overlaps the drain region 13.
The gate electrode 14 is formed in a substantially rectangular shape so as to overlap the gate insulating film 16. A long side of the gate electrode 14 extends in the Y direction and a short side thereof extends in the X direction.
FIG. 30 is a schematic sectional view taken along line A-A of the semiconductor device 10 of FIG. 29. As shown in FIG. 30, the semiconductor region 15 is formed on a main surface of a semiconductor substrate 17. In FIG. 30, the semiconductor region 15 and the semiconductor substrate 17 may be of the same conductivity type or of different conductivity types. Each of the element isolation region 11, the source region 12 and the drain region 13 has a certain depth from the main surface of the semiconductor region 15 in the Z direction. For example, the element isolation region 11 is formed to be deeper than the source region 12 and the drain region 13. In addition, a channel region ch is formed in the semiconductor region 15 between the source region 12 and the drain region 13. The end portions of the source region 12 and the drain region 13 are formed in contact with the element isolation region 11.
FIG. 31 is a schematic sectional view taken along line B-B of the semiconductor device 10 of FIG. 29. As shown in FIG. 31, a thickness ox of each of both end portions of the gate insulating films 16 at a boundary portion between the channel region ch and the element isolation region 11 in the Y direction, that is, the direction of the channel width W1 and the channel width W2, is smaller than those of other portions.
FIG. 32 is a schematic plan view showing a relationship between a main transistor and parasitic transistors in the semiconductor device 10 of FIG. 29. As shown in FIG. 32, the semiconductor device 10 includes a main transistor Q10, a parasitic transistor Q11 and a parasitic transistor Q12. The parasitic transistor Q11 and the parasitic transistor Q12 are formed at the boundary portion between the channel region ch and the element isolation region 11 in the Y direction, that is, the direction of the channel width W1 and the channel width W2. The main transistor Q10 is formed in the channel region ch in the semiconductor region 15 where the parasitic transistor Q11 and the parasitic transistor Q12 are not formed. In the semiconductor device 10, it is not possible to clearly delineate a boundary between the main transistor Q10 and the parasitic transistors Q11 and Q12. However, in the specification, for convenience of explanation, they are distinguished from each other in this way. The number of parasitic transistors is not limited to two but may be three or more.
FIG. 33 is a schematic equivalent circuit diagram of the semiconductor device 10 of FIG. 32. The sources, the drains and the gates of the parasitic transistor Q11 and the parasitic transistor Q12 are connected to the source, the drain and the gate of the main transistor Q10, respectively. That is, the main transistor Q10, the parasitic transistor Q11 and the parasitic transistor Q12 are connected in parallel in such a manner that the sources, drains and gates of the main transistor Q10, the parasitic transistor Q11 and the parasitic transistor Q12 form a common source S, a common drain D and a common gate G, respectively. The semiconductor device 10 is constituted by the common source S, the common drain D and the common gate G.
The gate thickness t10 of the main transistor Q10 is larger than the gate thickness t11 of the parasitic transistor Q11 and the gate thickness t12 of the parasitic transistor Q12 (t10>t11 (t12)). In this case, within a certain range of a gate width of the main transistor Q10, threshold voltages of the parasitic transistor Q11 and the parasitic transistor Q12 may be lower than a threshold voltage of the main transistor Q10. In addition, unlike the gate thickness t10 of the main transistor Q10, it is difficult to limit the gate thickness t11 of the parasitic transistor Q11 and the gate thickness t12 of the parasitic transistor Q12 to a certain range in manufacture. The thicknesses thereof are denoted by ox in FIG. 31.
Channel surface potentials of the parasitic transistor Q11 and the parasitic transistor Q12 are different from a channel surface potential of the main transistor Q10. Since gate insulating films of the parasitic transistor Q11 and the parasitic transistor Q12 are often made thin, thereby providing a low threshold voltage, a drain current (Id) flows in a state where a gate-source voltage (Vgs) is low. A drain current of the main transistor Q10 in a sub-threshold region may be smaller than the drain current of the parasitic transistor Q11 and the parasitic transistor Q12. A desired circuit operation obtained by controlling the drain current of the sub-threshold region of the main transistor Q10 may be inhibited by the drain current of the parasitic transistor Q11 and the parasitic transistor Q12.
FIG. 34 shows a gate-source voltage (Vgs)-drain current (Id) characteristic in the semiconductor device 10 of FIG. 29 and the equivalent circuit diagram of FIG. 33. In FIG. 34, symbol X denotes a curve showing a gate-source voltage (Vgs)-drain current (Id) characteristic of the parasitic transistor Q11 and the parasitic transistor Q12. Symbol Y denotes a curve showing a gate-source voltage (Vgs)-drain current (Id) characteristic of the main transistor Q10. As shown in the gate-source voltage (Vgs)-drain current (Id) characteristic curve, when the parasitic transistor Q11 and the parasitic transistor Q12 are present, in a weak inversion region, i.e., the sub-threshold region, where the gate-source voltage Vgs of the main transistor Q10 is small, the drain current of the parasitic transistor Q11 and the parasitic transistor Q12 is predominant over the drain current of the main transistor Q10. Therefore, with an increase in the gate-source voltage, when the parasitic transistor Q11 and the parasitic transistor Q12 reach a strong inversion region and the drain current of the weak inversion region of the main transistor Q10 which does not reach the strong inversion region exceeds the amount of current of the parasitic transistors, there occurs a hump (kink) phenomenon that the drain current Id suddenly increases.
As described above, a reverse narrow channel effect by the parasitic transistor Q11 and the parasitic transistor Q12 having a low threshold voltage occurs in the semiconductor device 10 shown in FIGS. 29 to 34. This may result in the electrical characteristics different from those expected for the main transistor Q10, thereby causing an unexpected circuit operation due to the parasitic transistor Q11 and the parasitic transistor Q12.
Next, another configuration of the semiconductor device in the related art will be described. FIG. 35 is a schematic plan view illustrating another configuration of the semiconductor device in the related art. FIG. 36 is a schematic sectional view taken along line C-C of the semiconductor device 20 of FIG. 35. FIG. 37 is a schematic sectional view taken along line D-D of the semiconductor device 20 of FIG. 35. FIG. 38 is a perspective sectional view taken along line E-E of the semiconductor device 20 of FIG. 35. FIG. 39 is a schematic plan view illustrating a main transistor and a parasitic transistor of the semiconductor device 20 of FIG. 35. FIG. 40 is a circuit diagram illustrating a relationship between the main transistor and the parasitic transistor of the semiconductor device 20 of FIG. 35.
Hereinafter, another configuration of the semiconductor device having a STI structure in the related art will be described with reference to the drawings. In FIGS. 35 to 39, as indicated by arrows X, Y and Z, three mutually orthogonal directions are defined as X, Y and Z directions, respectively. Throughout these figures, elements and parts or portions having the same functions are denoted by the same reference numerals or symbols and an explanation of which will not be repeated for the purpose of brevity and clarity.
As illustrated in FIG. 35, the semiconductor device 20 includes a transistor 20a and a transistor 20b. The transistor 20a includes a source region 22a, a drain region 23a, a gate electrode 24a, a semiconductor region 25 and a gate insulating film 26a. Like the transistor 20a, the transistor 20b includes a source region 22b, a drain region 23b, a gate electrode 24b, a semiconductor region 25 and a gate insulating film 26b. The transistor 20a and the transistor 20b have a symmetrical structure with line E-E in the Y direction as an axis.
The semiconductor region 25 is a region on which the source region 22a, the drain region 23a, the source region 22b and the drain region 23b are formed and also a region which is surrounded by an element isolation region 21. In a case of forming an NMOS transistor, the semiconductor region 25 is formed of the same P-type region as a silicon substrate.
The drain region 23a and the drain region 23b are formed adjacent to each other in a substantially rectangular shape on a main surface of the semiconductor region 25. The drain region 23a and the drain region 23b are electrically connected in common. A long side of each of the drain region 23a and the drain region 23b extends in the Y direction, that is, the direction of a channel width W3 and a channel width W4 and a short side thereof extends in the X direction, that is, the direction of a channel length L2a and a channel length L2b. An end portion of each of the drain region 23a and the drain region 23b in the Y direction is in contact with the element isolation region 21.
The source region 22a is formed in a substantially rectangular shape on the main surface of the semiconductor region 25 at a predetermined interval in the X direction with respect to the drain region 23a. Along side of the source region 22a extends in the Y direction and a short side thereof extends in the X direction. The source region 22b is formed in a substantially rectangular shape at a predetermined interval in the X direction with respect to the drain region 23a. A long side of the source region 22b extends in the Y direction and a short side thereof extends in the X direction. An end portion of each of the source region 22a and the source region 22b in the Y and X directions is in contact with the element isolation region 21.
The channel width W3 of the source region 22a in the Y direction and the channel width W4 of the drain region 23a in the Y direction are equal to each other. The channel width W3 of the source region 22b in the Y direction and the channel width W4 of the drain region 23b in the Y direction are also equal to each other. The channel length L2a from the end portion of the source region 22a in the X direction to the end portion of the drain region 23a in the X direction is equal to the channel length L2b from the end portion of the source region 22b in the X direction to the end portion of the drain region 23b in the X direction.
The element isolation region 21 is formed on the main surface of the semiconductor region 25 and inside the semiconductor region 25 so as to surround the source region 22a, the drain region 23a, the source region 22b and the drain region 23b. 
The gate insulating film 26a is formed in a substantially rectangular shape on an upper portion of the semiconductor region 25a between the source region 22a and the drain region 23a. Both end portions of the gate insulating film 26a in the Y direction are connected to the element isolation region 21. One end portion of the gate insulating film 26a in the X direction substantially overlaps the source region 22a. The other end portion of the gate insulating film 26a in the X direction substantially overlaps the drain region 23a. 
The gate insulating film 26b is formed in a substantially rectangular shape on an upper portion of the semiconductor region 25b between the source region 22b and the drain region 23b. Both end portions of the gate insulating film 26b in the Y direction are connected to the element isolation region 21. One end portion of the gate insulating film 26b in the X direction substantially overlaps the source region 22b. The other end portion of the gate insulating film 26b in the X direction substantially overlaps the drain region 23b. 
The gate electrode 24a is formed in a substantially rectangular shape so as to overlap the gate insulating film 26a. A long side of the gate electrode 24a extends in the Y direction and a short side thereof extends in the X direction. The gate electrode 24b is formed in a substantially rectangular shape so as to overlap the gate insulating film 26b. A long side of the gate electrode 24b extends in the Y direction and a short side thereof extends in the X direction.
FIG. 36 is a schematic sectional view taken along line C-C of the semiconductor device 20 of FIG. 35. As shown in FIG. 36, the semiconductor region 25 is formed on a main surface of a semiconductor substrate 27. In FIG. 36, the semiconductor region 25 and the semiconductor substrate 27 may be of the same conductivity type or of different conductivity types. Each of the source region 22a, the drain region 23a, the source region 22b, the drain region 23b and the element isolation region 21 has a certain depth from the main surface of the semiconductor region 25 in the Z direction. For example, the element isolation region 21 is formed to be deeper than the source region 22a, the drain region 23a, the source region 22b and the drain region 23b. A channel region ch is formed in the semiconductor region 25 between the source region 22a and the drain region 23a, and between the source region 22b and the drain region 23b. 
FIG. 37 is a schematic sectional view taken along line D-D of the semiconductor device 20 of FIG. 35. FIG. 37 is a sectional view of a boundary portion between the element isolation region 21, the source region 22a, the drain region 23a, the source region 22b and the drain region 23b in FIG. 35. Therefore, the thickness of the gate insulating film 26a shown in FIG. 37 is smaller than the thickness of the gate insulating film 26a shown in FIG. 36. In this way, a parasitic transistor Q21a and a parasitic transistor Q22a shown in FIGS. 39 and 40 to be described below are formed in a portion ox where the thickness of the gate insulating film 26a is small. In addition, the thickness of the gate insulating film 26b is smaller than the thickness of the gate insulating film 26b shown in FIG. 36. In this way, a parasitic transistor Q21b and a parasitic transistor Q22b shown in FIGS. 39 and 40 to be described below are formed in a portion ox where the thickness of the gate insulating film 26b is small. When the thicknesses of the gate insulating film 26a and the gate insulating film 26b become small, threshold voltages of the gate insulating film 26a and the gate insulating film 26b are accordingly lowered.
FIG. 38 is a perspective sectional view taken along line E-E of the semiconductor device 20 of FIG. 35, showing the transistor 20a. As shown in FIG. 38, the transistor 20a includes the source region 22a, the drain region 23a, the gate electrode 24a, the gate insulating film 26a and the semiconductor region 25. An end portion of the drain region 23a in the X direction is in contact with the element isolation region 21. The configuration that the end portion of the drain region is in contact with an element region is the same as, e.g., one example of the related art shown in FIG. 32. In addition, although a relationship in boundary portion between the source region 22a and the element isolation region 21 in the respect of a section is not shown in FIG. 38, an end portion of the source region 22a is in contact with the element isolation region 21.
FIG. 39 is a schematic plan view showing a relationship between a main transistor and a parasitic transistor of the semiconductor device 20 of FIG. 35. As shown in FIG. 39, the transistor 20a includes a main transistor Q20a, a parasitic transistor Q21a and a parasitic transistor Q22a. The transistor 20b includes a main transistor Q20b, a parasitic transistor Q21b and a parasitic transistor Q22b. The parasitic transistor Q21a and the parasitic transistor Q22a are formed at the boundary portion between the channel region ch and the element isolation region 21 in the Y direction of the transistor 20a, that is, the direction of the channel width W3 and the channel width W4. The main transistor Q20a is formed between the parasitic transistor Q21a and the parasitic transistor Q22a. The parasitic transistor Q21b and the parasitic transistor Q22b are formed at the boundary portion between the channel region ch and the element isolation region 21 in the Y direction of the transistor 20b. The main transistor Q20b is formed in the channel region ch in the semiconductor region 25 where the parasitic transistor Q21b and the parasitic transistor Q22b are not formed. In the semiconductor device 20, it is not possible to clearly delineate a boundary between the main transistors Q20a and Q20b and the parasitic transistors Q21a, Q22a, Q21b and Q22b. However, in the specification, for convenience of explanation, they are distinguished from each other in this way. The number of parasitic transistors is not limited to four but may be fewer or more.
FIG. 40 is a schematic equivalent circuit diagram of the semiconductor device 20 of FIG. 39. The sources, the drains and the gates of the parasitic transistor Q21a and the parasitic transistor Q22a are connected to the source, the drain and the gate of the main transistor Q20a, respectively. That is, the main transistor Q20a, the parasitic transistor Q21a and the parasitic transistor Q22a are connected in parallel. The sources and the gates of the main transistor Q20a, the parasitic transistor Q21a and the parasitic transistor Q22a form a common source S and a common gate G, respectively.
In addition, the sources, the drains and the gates of the parasitic transistor Q21b and the parasitic transistor Q22b are connected to the source, the drain and the gate of the main transistor Q20b, respectively. That is, the main transistor Q20b, the parasitic transistor Q21b and the parasitic transistor Q22b are connected in parallel. The sources and the gates of the main transistor Q20b, the parasitic transistor Q21b and the parasitic transistor Q22b form a common source S and a common gate G, respectively.
Further, the drain of the main transistor Q20a and the drain of the main transistor Q20b are interconnected. That is, the drains of the main transistor Q20a, the parasitic transistor Q21a, the parasitic transistor Q22a, the drain of the main transistor Q20b, the parasitic transistor Q21b and the parasitic transistor Q22b form a common drain D. The semiconductor device 20 is constituted by the common source S, the common drain D and the common gate G.
The gate thickness t20a of the main transistor Q20a is larger than the gate thickness t21a of the parasitic transistor Q21a and the gate thickness t22a of the parasitic transistor Q22a (t20a>t21a (t22a)). In this case, within a certain range of a gate width of the main transistor Q20a, threshold voltages of the parasitic transistor Q21a and the parasitic transistor Q22a may be lower than a threshold voltage of the main transistor Q20a. In addition, unlike the gate thickness t20a of the main transistor Q20a, it is difficult to limit the gate thickness t21a of the parasitic transistor Q21a and the gate thickness t22a of the parasitic transistor Q22a to a certain range in manufacture. The thicknesses thereof are denoted by ox in FIG. 31.
The gate thickness t20b of the main transistor Q20b is larger than the gate thickness t21b of the parasitic transistor Q21b and the gate thickness t22b of the parasitic transistor Q22b (t20b>t21b (t22b)). In this case, within a certain range of a gate width of the main transistor Q20b, threshold voltages of the parasitic transistor Q21b and the parasitic transistor Q22b may be lower than a threshold voltage of the main transistor Q20b. In addition, unlike the gate thickness t20b of the main transistor Q20b, it is difficult to limit the gate thickness t21b of the parasitic transistor Q21b and the gate thickness t22b of the parasitic transistor Q22b to a certain range in manufacture. The thicknesses thereof are denoted by ox in FIG. 31.
Channel surface potentials of the parasitic transistor Q21a and the parasitic transistor Q22a are different from a channel surface potential of the main transistor Q20a. Since gate insulating films of the parasitic transistor Q21a and the parasitic transistor Q22a are often made thin, thereby providing a low threshold voltage, a drain current (Id) flows in a state where a gate-source voltage (Vgs) is low. A drain current of the main transistor Q20a in a sub-threshold region may be smaller than the drain current of the parasitic transistor Q21a and the parasitic transistor Q22a. A desired circuit operation obtained by controlling the drain current of the sub-threshold region of the main transistor Q20a may be inhibited by the drain current of the parasitic transistor Q21a and the parasitic transistor Q22a. 
Channel surface potentials of the parasitic transistor Q21b and the parasitic transistor Q22b are different from a channel surface potential of the main transistor Q20b. Since gate insulating films of the parasitic transistor Q21b and the parasitic transistor Q22b are often made thin, thereby providing a low threshold voltage, a drain current (Id) flows in a state where a gate-source voltage (Vgs) is low. A drain current of the main transistor Q20b in a sub-threshold region may be smaller than the drain current of the parasitic transistor Q21b and the parasitic transistor Q22b. A desired circuit operation obtained by controlling the drain current of the sub-threshold region of the main transistor Q20b may be inhibited by the drain current of the parasitic transistor Q21b and the parasitic transistor Q22b. 
As described above, since the semiconductor device 20 shown in FIGS. 35 to 40 includes the parasitic transistor Q21a, the parasitic transistor Q22a, the parasitic transistor Q21b and the parasitic transistor Q22b, a reverse narrow channel effect and a hump (kink) phenomenon occur in the semiconductor device 20. This may result in the electrical characteristics different from those expected for the main transistor Q20a and the main transistor Q20b, thereby causing an unexpected circuit operation due to the parasitic transistor Q21a, the parasitic transistor Q22a, the parasitic transistor Q21b and the parasitic transistor Q22b. 
A variety of measures has been adopted to solve the above problems.
In the semiconductor devices disclosed in the related art, a silicon oxide film (SiO2 film) filling an element isolation trench constituting the STI structure is formed so as to extend outside the element isolation trench on a substrate surface and project slightly upward from the substrate surface. Thus, even when a gate electrode extends over the SiO2 film, no electric field concentration occurs in the substrate, thereby avoiding a problem of a variation in a threshold voltage.
In the semiconductor devices disclosed in the related art, by making a difference in shape between an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) and a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor), a balance with a lateral distribution of channel impurities occurred by a thermal process is kept to prevent a threshold voltage near the top portion of an element isolation trench from differing from a threshold voltage near a gate electrode central portion. This makes it possible to suppress a reverse narrow channel effect which occurs when the element isolation trench is formed, and a reverse channel effect of PMOS at once. Further, this makes it possible to prevent a hump (link) phenomenon from occurring in a sub-threshold region.
In the semiconductor devices disclosed in the related art, since an inclination of a trench side wall located in a channel corner portion covered with a gate electrode of a transistor is made smooth, it is possible to mitigate a concentration of an electric field from the gate electrode and prevent lowering of a threshold voltage of a channel corner portion of a transistor peculiar to an STI structure.
In the semiconductor devices disclosed in the related art, a channel edge portion below a gate of a MOS transistor is out of a region into which high concentration impurity ions used to form a source-drain region are implanted. Since the channel edge portion exists out of an operation region of the MOS transistor, no hump (kink) phenomenon occurs.
In the semiconductor devices disclosed in the related art, an element formation region or a gate electrode is shaped such that an effective resistance is higher near a boundary between the element formation region and an element isolation region than at the channel center. This reduces an effect of a channel portion having a low threshold value on a drain current.
In the semiconductor devices disclosed in the related art, since a SiO2 film is formed to slightly project upward from a substrate surface, it makes a process of manufacturing a semiconductor device more complicated while increasing the number of processes of manufacturing the semiconductor device.
In the semiconductor devices disclosed in the related art, since a balance with a lateral distribution of channel impurities is kept by making a difference in shape between an NMOS and a PMOS to prevent a threshold voltage near the top portion of an element isolation trench from differing from a threshold voltage near a gate electrode central portion, it makes a process of manufacturing a semiconductor device more complicated while increasing the number of processes of manufacturing the semiconductor device.
In the semiconductor devices disclosed in the related art, since there is a need to smoothen an inclination of a trench side wall located in a channel corner portion covered with a gate electrode of a transistor, it makes a process of manufacturing a semiconductor device more complicated while increasing the number of processes of manufacturing the semiconductor device.
In the semiconductor devices disclosed in the related art, an active region other than a high concentration impurity ion implantation region is exposed. Therefore, the exposed active region may be field-inverted due to an effect by other electric fields, which may cause a hump (kink) phenomenon.
In the semiconductor devices disclosed in the related art, an element formation region or a gate electrode is shaped such that an effective resistance is higher near a boundary between the element formation region and an element isolation region than at the channel center. In this case, it is necessary to adjust the shape of the element formation region or the gate electrode, which makes a process of manufacturing a semiconductor device more complicated while increasing the number of processes of manufacturing the semiconductor device.
In the above-described semiconductor devices disclosed in the related art, measures to suppress the reverse narrow channel effect and the hump (kink) phenomenon have been taken. However, these measures have a problem in that these make a process of manufacturing a semiconductor device more complicated in some aspects.